Dr. Régis Leveugle

Dr. Régis Leveugle received the PhD degree in Microelectronics from the National Polytechnical Institute of Grenoble (INPG), France, in 1990. He is currently Professor at this institute and member of TIMA laboratory. His main interests are computer architecture, VLSI design methods and CAD tools, dependability evaluation, faulttolerant architectures, concurrent checking and secure circuit design.

He has 20 years experience in teaching VLSI design, test and dependability. He created four years ago a specific lecture at Master level on the subject of the proposed tutorial. He also presented several tutorials and embedded tutorials in IEEE international conferences on dependability- and security-related subjects (DTIS'06, ICECS'06, ICECS'07, ICECS'08, SCS'09, LASCAS'10). He was co-author of an embedded tutorial on "Ensuring high testability without degrading security" at the 14th IEEE European Test Symposium, Sevilla, Spain, May 2009. He has authored or co-authored more than 150 scientific papers and served as a reviewer for many journals and conferences. He has been a member of the French evaluation committee for national projects on security. He has also served on more than 80 international conference program and organization committees. He was Program co- Chair for the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), vice- General Chair for the 2002 IEEE International On-Line Testing Workshop, General co-Chair for DFT'02, vice- Program Chair for the 2003, 2005 and 2007 IEEE International On-Line Testing Symposium (IOLTS) and Program co-Chair for IOLTS'03 and IOLTS'06. He is a member of IEEE.